Design-Reuse

True Circuits Introduces Delay-Locked Loop Hard Macros

Silicon Proven Low-Jitter DLLs Target High-Speed DDR Style Interface Applications LOS ALTOS, California, October 8, 2003 - True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal ...
Nature

Delay-Locked Loop Design and Applications

Delay-locked loops (DLLs) are critical components in modern electronic systems, providing robust synchronisation of clock signals in a variety of applications ranging from high-speed communication to ...
EDN

Delay- and phase-locked loops becoming reusable IP

San Mateo, Calif. – Phase-locked and delay-locked loops are becoming increasingly important weapons in the system-on-chip design arsenal, but PLLs and DLLs are notorious for their difficulty. Now, ...
EDN

Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new ...