IEEE

An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS

Abstract: This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc–dc switched-capacitor voltage regulator (SCVR). The ...
IEEE

A RISC-V-Based High-Throughput Accelerator for Sparse Winograd CNN Inference on FPGA

Abstract: This letter proposes a RISC-V-based accelerator for inferring a model that uses efficient sparse Winograd convolutional neural networks. This accelerator consists of a RISC-V processor ...
GitHub

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

This project implements a multicycle RISC-V processor using SystemVerilog. It is designed to execute a subset of the RISC-V instruction set architecture (ISA) and demonstrates a step-by-step ...