GitHub

Verilog Generation with Reinforcement Learning

This repository contains the code and data for training a Verilog generation model using reinforcement learning (RL) with feedback from testbenches. The goal is to improve the quality of generated ...
IEEE

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

Abstract: The rapid adoption of large language models (LLMs) in hardware design has primarily focused on generating functionally correct Verilog code, overlooking critical Power-Performance-Area (PPA) ...
IEEE

Implementation of 8-Bit SPI Protocol Using System Verilog and UVM

Abstract: Currently, the design and verification of efficient communication protocols are essential in embedded systems. This paper focuses on the development and verification of an 8-bit Serial ...
GitHub

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

This project implements a multicycle RISC-V processor using SystemVerilog. It is designed to execute a subset of the RISC-V instruction set architecture (ISA) and demonstrates a step-by-step ...