IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Design of a Novel Active Gate Drive Circuit to Enhance Current Sharing in Parallel-Connected MOSFETs for Low-Voltage Inverter Applications

Abstract: Low-voltage systems offer advantages in terms of safety, cost-effectiveness, and ease of integration, making them a preferred choice for e-scooters, light electric vehicles (LEVs), and ...
GitHub

Design-Implementation-of-an-8-bit-Cryptosystem-using-VSDSquadron-FPGA-Mini

Theme:Cryptographic Hardware Engines Idea:The main purpose of this project is to Design and Implement an 8-bit Cryptosystem using VSDSquadron FPGA Mini. Target output:A select line is used to ...
GitHub

pravesh-sandal/Digital-IC-Design-Journey-with-cadence-virtuoso

Welcome to my personal journey into Digital IC Design using Cadence Virtuoso and 45nm CMOS technology. This repository documents my day-by-day learning and design progress, covering the complete ...