IEEE

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

Abstract: This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transceiver (TRX) for extra-short-reach (XSR) applications in 28-nm CMOS. The receiver (RX) adopts a 4 × 6 time ...
IEEE

A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration

Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...