IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
GitHub

cmos-logic

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean ...
IEEE

High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process

Abstract: This study introduces a breakthrough achievement of 0.1-Gb/mm2 wing-shaped high-density embedded 3-D via resistive random access memory (Via RRAM) in TSMC’s 16-nm FinFET CMOS logic process.